AMD GPU Performance Engineer

AMD GPU Performance Engineer Location: Remote Role Overview We are looking for an AMD GPU Performance Engineer to optimize vLLM inference performance across the AMD accelerator ecosystem. This role focuses on developing and optimizing GPU backends, kernels, runtime paths, and benchmarking infrastructure using ROCm, HIP, Triton, CK, and AITER. The ideal candidate will have deep knowledge of AMD GPU architecture, kernel optimization, performance profiling, and LLM inference systems.

Key Responsibilities

Build and optimize AMD GPU backends, kernels, and runtime paths for vLLM. Optimize performance-critical operations, including attention, GEMM, sampling, KV cache, and communication-heavy workloads. Develop and improve GPU kernels using ROCm, HIP, Triton, CK, AITER, and related tools. Profile GPU workloads and identify bottlenecks across memory behavior, execution, and runtime performance. Build and maintain benchmarking infrastructure to measure inference performance and detect regressions. Use hardware counters, correctness tests, and reproducible benchmarks to guide optimization. Improve the usability, performance, and maintainability of AMD GPU support in vLLM. Optimize inference paths involving batching, decoding, quantization, and memory management.

Required Qualifications

Bachelor's degree or equivalent experience in Computer Science, Engineering, Systems, Machine Learning, or a related field. Hands-on experience optimizing AMD GPU workloads using ROCm, HIP, Triton, CK, AITER, or similar tools. Deep understanding of AMD GPU execution, memory behavior, toolchains, and kernel performance. Experience optimizing ML kernels or inference paths such as attention, GEMM, sampling, KV cache, and fused kernels. Strong performance profiling and benchmarking skills. Ability to use hardware counters, correctness tests, and reproducible benchmarks to guide optimization.

Preferred Qualifications

Experience with vLLM, SGLang, TensorRT-LLM, ROCm-based serving, or other LLM inference systems. Familiarity with batching, KV cache, decoding, and production inference serving tradeoffs. Knowledge of compiler and kernel technologies such as Triton, MLIR, LLVM, CK, AITER, and HIP. Experience with INT8, FP8, mixed-precision, or AMD-specific numeric formats, including accuracy and performance tradeoffs.