ASIC Design Engineer
Location: Bay Area, CA (hybrid, on-site a few days/week) — remote considered for the right candidate Type: Full-time Department: Hardware / Silicon
About the Role
A high-performance silicon team is building next-generation ASICs/SoCs for large-scale AI and ML workloads. We're hiring silicon micro-architects and design engineers to own performant, functionally accurate silicon across compute, memory management, and high-speed connectivity, from micro-architecture through sign-off.
What You'll Do
Contribute to a scalable architecture-to-design methodology spanning blocks, subsystems, and full-chip design Own subsystem and/or chip-level design deliverables end to end, from micro-architecture through sign-off-ready RTL Plan and drive intermediate and sign-off reviews covering micro-architecture, design specs, execution progress, and area/timing closure toward design freeze and tapeout Partner closely with verification, DFT, and physical design co-owners to deliver best-in-class PPA (performance, power, area)
What We're Looking For
Concept-to-silicon experience driving subsystem and/or top-level ASIC/SoC design from architecture spec to production silicon 5+ years with SystemVerilog, Python, and C/C++ (and related scripting/programming for chip design flows) Production-proven micro-architecture and design experience in high-performance compute (CPUs, GPUs, accelerators), high-speed connectivity, and/or memory management Hands-on with design synthesis, equivalence checking, lint, and clock-domain-crossing flows to reach high-quality sign-off Solid grasp of DFT and physical design concepts, working alongside specialists to close timing, power, area, and test coverage Experience collaborating with verification teams toward performance and coverage closure
Nice to Have
Familiarity with verification, emulation platforms, and methodologies Silicon debug and bring-up experience Hands-on silicon/firmware experience with PCIe, HBM, DMA, or die-to-die subsystems
Compensation
Competitive base scaled by experience level, from roughly $160K to $600K , plus meaningful equity. Strong benefits package including generous PTO, subsidized medical/dental/vision, 401(k) match, parental leave, professional development budget, and commute/home-office support. Please Note This role requires access to information subject to U.S. export control regulations. Candidates must be able to perform the role in compliance with U.S. export control laws.